Подборка наиболее интересных статей по проектированию встраиваемых систем с DSP процессорами, опубликованных в 2008 и 2007 гг.

**2008 год**

DSP Tricks: Frequency translation using decimation

Here is a tip on how to do freguency translation using decimation.

Analyzing DSP networks with Mason’s Rule

Here is an easy way to obtain the z-domain transfer function of a DSP network (DSP block diagram)

The math of DSP: Part 5 — Orthogonality

Explained is the concept of orthogonality and the concept of quadrature signals is introduced.

The math of DSP: Part 4 — Convolution, Fourier and Nyquist

Explained are the details of convolution and Fourier series calculations and the Nyquist sampling theorem

The math of DSP: Part 3 — Filters

The basics of low-pass and high-pass filsters and an explanation of the concept of causeality.

DSP Tricks: DC removal

Some tips on block data DC removal, real time DC removal and real time DC removal with quantization.

The math of DSP: Part 2 — Complex numbers

Topics covered are real and imaginary numbers, periodic signals, digital frequencies and discret arithmetic.

The math of DSP: Part 1 — Series, integration and frequency

The basic math for DSP, including polynomials, transcendentals, series, limits, integration, polar notation and frequency.

DSP Tricks: Efficient polynomial evaluation

Here are some tips on on efficial polynomial evaluation

Analysis: Freescale’s six-core DSP

BDTI examines Freescale’s new six-core DSP chip, the MSC8156, which targets wireless base stations.

Combining DSP and MCU operations in computationally complex time-critical apps

A Product How-To on using the Fujitsu 91470 MCU/DSP combo for digital filter apps that evaluate systems states and carry out fast loops

What’s your sine?

A new approach to direct digital frequency uses a combination of lookup tables and trig identities that lends itself to more efficient implementation on DSPs.

DSP Tricks: Smoothing impulsive noise

Some tips on smoothing impulsive noise by using a technique originally used to detect microampere changes in milliampere signals.

Optimizing video analytics on a DSP

Here’s how to implement both video compression and analytics on a single DSP. Topics covered include algorithm, memory and code optimization.

Speeding up the CORDIC algprothm with a DSP

When a CORDIC algorithm is implemented on a DSP, can the multipliers improve CORDIC performance?

DSP Tricks: Interpolating a bandpass filter

Some tips on interpolating a bandpass signal

Architecture oriented C optimization techniques: Part 2 — Memory and more

How to optimize C for memory alignment, cache features, endianness and application specific instructions.

Implement dual OS signal processing with Linux and the DSP/BIOS RTOS

In mixed signal DSP/GPU environents use a system virtual machine to run both Linux and the DSP/BIOS RTOS concurrently on the same DSP processor.

DSP Tricks: Interpolating a bandpass signal

Some tips on the interpolation of a bandpass signal.

DSP Tricks: Spectral leak location algorithm

A useful way to estimate the frequency of a sinusoid or the center frequency of a very narrowband signal.

Using programmable logic for efficient and effective DSP design

With an FPGA front-end that allow access to the latest I/O technology, as well as IP blocks for the latest standards, designers have flexibility to choose the right interfaces without making changes to the DSP software.

Asynchonous DSPs: Low power, high performance

An acynchronous DSP offers better power, performance and reliability than one based on standard synchronous logic, enabling simpler and less expensive PCB and power supply design.

DSP system design: Part 2 — Critical design choices

How to choose hardware and software architectures, how to choose an RTOS and how algorith and I/O libraries impact the development process.

DSP system design: Part 1 — The basic laws

Ten laws that yout can use to guide DSP system developing including such topics as economies of scale and experience effect, DSPs vs. FPGAs, fixed- vs. floating-point and RTOSes and algorithm libraries.

Signal processing on the MIPS 74K

BDTI evaluates the signal processing features of MIPS high performance superscalar core, the 74k.

DSPs versus FPGAs for multiprocessing

Here’s whats available for high performance multiprocessor systems and how to make the best choice between DSP, FPGA or a hybrid of the two.

Avoiding noise and EMI problems in DSP systems

Noise and EMI can disrupt the operation of a DSP system or cause the design to fail FCC certificqtion. Here is how to avoid these problems with PCB layou and return path coupling.

Modulation roundup: error rates, noise and capacity

A comparison of various digital signal modulation schemes such as BPSK, QPSK, PAM, 16PSK, 32PSK, 16QAM and 64QAM using a variety of metrics.

DSP Tricks: Computing FFT twidle factors

Some useful tricks for computing Fast Fourier Transform twiddle factors.

Frequency domain toutorial: Part 2 — Complex signals and spectral diagrams

Building on the basics introduced in Part 1, this article introduces the concept of quadrature (complex) signals and explains the nature and notation of the spectral diagrams used in DSP.

Freguency domain tutorial: Part 1 — Dealing with ambiguity

What you need to know about the mathematics and notation of FFTs and the discrete frequency domain, starting with how to deal with discrete signal ambiguities.

Speaker equalization using FIR filters

Pros and cons of using FIR filters for speaker equalization versus DSP-, MCU- and FPGA-based approaches.

DSP Tricks: A/D conveter testing techniques and finding missing codes in ADCs

Some tricks for using DSP techniques to test A/D converters and some tips on how to detect missing codes in ADCs.

Symbol error rate for M-QAM modulation

Krishna Pillai shows how to calculate the error rate for modulation schemes such as QPSK, 16-QAM, 64-WAM and provides a MATLAB/Octave scripts for computing symbol error rate.

Making design choices between DSPs and FPGAs

Design guidelines on how to choose between DSPs and FPGAs or a combination of the two taking into account device cost, performance, NRE and availability of application-specific features.

Multirate DSP: Part 2 — Noninteger sampling facors

How to change the sampling rate by a noninteger factor as well as multistate decimation and polyphase filters as will as application of up/down sampling to a CD player application.

DSP Tricks: Reducing A/D converter quantization noise

How to use oversampling and dithering to reduce analog to digital conversion quantization noise.

Multirate DSP: Part 1 — Upsampling and downsampling

Part 1 introduces the concepts of multirate signal processing, explaining how to upsample and downsample by an integer factor. MATLAB code included.

How to implement DSP algorithms using the Spartan-3E FPGA starter board

This «How-to» is an excerpt from «Embedded Design using Programmable Gate Arrays»

**2007 год**

DSP Tricks: Fast multiplication of complex numbers

Here is a quick and easy way to do fast multiplication of complex numbers.

Combining C code with assembly code in DSP applications

Here’s how to integrate assembly code into C, including such topics as compiler conventions, inlining, intrinics, register binding and debug strategies.

Digital Signal Processing Tricks: High speed vector magnitude approximation.

Richard Lyons takes on high speed vector magnitude approximation in another in an ongoing series of DSP design hints and tricks.

Ensuring high quality video communications

As the migraton to high definition picks up speed, video system designers are facing new challenges relation to DSP bandwidth requirements, image quality, transcoding and digital media codec flexibility.

Multichip architectures partition H.264 tasks for high quality video

For high quality video enconding, transcoding, transrating and decoding, multiprocessing devices are necessary. Here are some tips on distributing the tasks among multiple DSPs and FPGAs.

Using mixed signal DSPs in embedded control applications.

Dr. Finbarr Moynihan describes how changing demands for embedded control have lead to the development of single chip devices based on core competencies in digital signal processing

BDTI benchmarks picoChip PC102

BDTA has released the first independent benchmark results comparing picoChip’s massively parallel PC102 chip to that of high performance DSPs and FPGAs.

Fundamentals of embedded video: Part 5

The final part in this series takes a look at a sample video applications, touching on the major DSP and processing blocks involved.

Fundamentals of embedded video: Part 4

Part 4 in this series looks at video flows from a processor or DSP standpoint, focusing on features that enable efficient data manipiulation and movement.

Fundamentals of embedded video: Part 3

Part 3 in this series looks at video flows from a system level, discusses the types of video sources and displays that compromise an embedded video application.

Fundamentals of embedded video: Part 2

Part 2 in this eries discusses color spaces and gamma correction and explains the basics of digital video.

Fundamentals of embedded video: Part 1

The first part in this series explains how video signals are tailored to the human vision system and reviews the basics of NSTC and PAL video signals.

Infrastructure DSPs for the triple play era

Emerging voice/data/media networks requre a combination of high performance and high speed I/O Here’s how to pick a DSP that will do all this and provide a cost effective solution as well.

Fundamentals of embedded audio: Part 3

The final part in this series reviews data management schemes such as double buffering and DMA transfers and then discusses the basics of audio algorithms.

Fundamentals of embedded audio: Part 2

Part 2 in this three part series discusses numeric formats as they relate to audio processing, with a focus on dynamic range and precision.

Fundamentals of embedded audio: Part 1

Part 1 in this series explains how processors and DSPs interface with audio signals with a focus on the basics of audio converters and common peripheral standards for connecting these devices.

ADCs for DSP Applications — Part 4

Part 4 in this series exampines jitter, delay and other errors in ADCs.

ADCs for DSP Applications — Part 3

Part 3 in this series continues the discussion of sigma-delta ADCs with a loop at oversampling, bit scrambling and dynamic range.

ADCs for DSP Applications — Part 2

Part 2 in this series explains how sigma-delta analog-digital converters work, covering quantization, noise shaping, and calculating the effective number of bits.

ADCs for DSP Applications — Part 1

Part 1 of this five part series gives an overview of the most popular ADCs for DSP: successive approximation, sigma-delta flash, subranging (or pipelined) and bit per stage (ripple).

Revisiting homegeneous versus heterogeneous

Jeff Bier looks at the trade-offs in using homogeneous versus heterogeneous processing elements in multi-core chips for DSP applications.

FFT convolution and the overlap add method

For long filters, FFT convolution is faster than standard convolution. Here is how it works and how the overlap-add method plays a role.

Digital Signal Processing Tricks — Frequency Translation without multiplication

Richard Lyons takes on frequency translation without multiplication in the first of an on-going series of DSP design hints and tricks focused on creative techniques that professionals can use to make their digital signal processing algorithms more efficient.

Top down DSP design for FPGAs

High level C++ synthesis in combination with FPGAs is an attractive solution for achieving a rapid path from C++ to RTL running in hardware.

Fundamentals of embedded audio: Part 3

This part in a series on embedded audio reviews data management schemes such as double buffering and DMA transfers and then discusses the basics of audio algorithms.

Fundamentals of embedded audio: Part 2

This part in a series on embedded audio algorithms discusses numeric formats as they relate to audio processing, with a focus on dynamic range and precision.

Fundamentals of embedded audio: Part 1

This first in a series on embedded audio algorithms explains how processors interface with audio signals as well as delves into the basics of audio converters and the common peripheral standards for connecting to these converters.

Ultra-low-power DSP design

Here’s how IMEC built a sub-100 uW DSP by tuning its algorithm, processor architecture and memory system, as well as through clock gating. The article presents detailed power results for each optimizaion.

DSP Silicon takes on many forms

Here’s a guide to the chips used in signal processing: DSPs, MPUs, FPGAs, multiprocessors, massively parallel processors and more.

Compiler optimization for DSP applications

Here’s how to use compilation options to improive performance in DSP applications.

DSP serves the convergence needs of small businesses

For OEMs, selecting the right technology can make it easier to reach small and medium sized businesses with new devices for converged voice, video, and data services.

Wideband vs narrowband VoIP codecs

Here’s how wideband and narrowband G.7xxx codecs compare in terms of voice quality, band width requirements and computational loading.

Analysis: 1 GHz MIPS core is DSP speed demon

The new MIPS 74L targets demanding applications like H.264. Here’s how it works, and how it compares to the competition.

Implementing floating point DSP on FPGAs

Here’s how to use PicoBlaze processors for high performance, power-efficient floating point DSP.

Desiging FFTs for cache-based DSPs

Here’s how to get the best FFT performance out of a chache-based DSP.

Massively parallel processors for DSP, Part 1

In this two part series, BDTI explains why you should consider massively parallel processors and what to look like in these chips, looking at the inner workings of processors like IBM’s Cell, Stretch’s reconfigurable cell and Mathstar’s FPOA.

How Video Compression works

Explained here is how video codec software algorithms like MPGE-4 and H.262 work and how they differ as well as the demands they make on general purposed and digital signal processors.

Analysis: How Tensilica’s D1 video engine works

Tensilica’s latest DSP-based video engine can do both H.264 and MPEG-4 encoding at D1 resolution. BDTI explains how it works.

Analysis: CEVA’s 32-bit, dual MAC Teaklite-III DSP

CEVA has soupted up its Teak core for audio and 3G applications. Here’s how it works and how it compares to the competition.

DSCs fuel the green revolution

Digital signal controllers are a new class of processor that combines the best attributes of micorocontrollers and digital signal processors.

Back to the basics: Tested and effective methods for speeding up DSP algorithms

In this brief tutorial, Ninin Jain of Mindtree provides a wealth of useful tips on speeding up your DSP code and your application through both source and algorithm level optimizations.

Graphical programming for DSPs

Graphical programming can help you reduce time to market, improve code reuse and port your design to multiple platforms. Here’s how.

Next generation VoIP and the role of DSP

Emerging technologies such as high definition voice are expanding the role of the IP phone. Here’s how to choose a DSP platform that can keep up with the changes.

Analysis: Hypercore touts 256 CPUs per chip

Plurality’s Hypercore supports up to 256 SPARC CPUs on a single IC. BDTI explains how it works and what it will take for the chp to succeed.

Multicore trend a challenge to DSP vendors

There’s been a lot of press about start-up companies offering multicore-DSP chips. What’s less discussed is that DSP chip vendors have been offering mult-core DSPs for some time.

DSP benchmark bamboozles

The changes in signal processing applications are making DSP vendors meet new demands while still addressing the old ones — or risk being marginalized in their own markets.

Real time operating systems for DSP, Part 8

In this final part in a series, you learn how to analyze systems with aperiodic tasks as well as understnd the dangers of priority inversion and how to avoid it using priority inheritance.

Real time Operting systems for DSP, Part 7

Part 7 of this 8-part series shows how to analyze scheduling behavior, and to ensure tasks meet their deadlines. It also shows how to account for interrupt latency and context switching overhead.

Realtime Operating systems for DSP, Part 6.

Part 6 of this 8-part series reviews various RTOS scheduleing algorithms — including both static and dynamic scheduling algorithms — and explains the pros and cons of each.

Equivalent results: A methodology to measure the effects of high speed compression.

Real-world examples demo the benefits of using appropriate compression, such as lower pin counts, power consumption and system costs as well as reduced board area.

Analysis: BDTI releases ARM Cortex-A8 benchmarks

The Cortex-A8 achieves impressive performance in BDTI’s video and signal procesing benchmarks, about 2X the performance of an ARM11.

Analysis: Xilinx Spartan gets DSP

BDTI explains how the new Spartan FPGAs from Xilinx can offer substantial DSP performance at lower cost and compares the new offering to its previous Virtex-4 and Virtex-5.

Real-Time Operating Systems for DSP, Part 5

In Part 5, details are provided on how to protect critical code and resources using semaphores, spin locks and other techniques. Also explained is how to synchronize independent tasks.

Real-Time Operating Systems for DSP, Part 4

In this segment in an eight part series, Robert Oshana of TI shows how to detect and recover from a deadlock, how to avoid unsafe states and how to avoid corruption of shared resources.

Real-Time Operating Systems for DSP, Part 3

In this third of an eight part series, the focus is on the RTOS kernel and how it prioritizes tasks. Also explained are memory allocation, system calls and hardware concepts.

A simple, efficient FFT implementation in C++, Part 1

This article, first in a series, describes a new efficient implementation of the Cooley-Tukey fast Fourier Transform )FFT) algorithm using C++ template metaprogramming.

Real-Time Operating Systems for DSP, Part 2

In the second part in this eight part series, Robert Oshana introduces the concept of multitasking and how an RTOS schedules tasks for execution.

Testing and Debugging DSP systems, Part 6

The final part in this series reviews the common bugs found in DSP applications and outlines different testing methods for finding these bugs.

Comparing mainstream DSP processors: a survey

Analyzed are digital signal processors form Analog Devices, Freescale and Texas Instruments including low cost fixed point, high performance fixed point and floating point DSPs.

Analysis: TI’s DaVinci Evaluation Module

Here is an excerpt from a report that BDTI did based on its hands on evaluation of Texas Instrument’s Digital Video Evaluation Module (DVEVM).

Analysis: Stretch’s second gen configurable DSP engine

The S6000 is a RISC processor incorporating a configurable multicore compute fabric of multiple DSP elements within its data path. Explained here is how it works and how it compares to more traditional processors.

Programmable DSP processors: Make them all, or one?

A pivotal question for the current crop of DSP and multicore startups is whether to offer their processors as flexible general purpose chips or as highly specialized, application specific designs.

Program and optimize DSP C code: Part 5

Part five of this five-part series shows how to optimize memory performance, and how to make speed vs. size tradeoffs.

Testing and Debugging DSP Systems, Part 5

Part five introduces the concepts of real-time data collection and data visualization. It also explains how compiler options affect the debugging process.

Testing and Debugging DSP Systems, Part 4

Part four explains how to use breakpoints, event triggers, and program traces to debug code.

Programming and optimizing C code, Part 4

Part 4 explains why it is important to optimize «control code,» and shows how to do so.

Testing and Debugging DSP Systems, Part 3

This article explains how emulation effectively imitates the DSP processor in its electrical characteristics and performance.

Programming and optimizing DSP C code: Part 3.

Part 3 explains how to access DSP features like hardware loops and circular addressing from portable C. It also shows how to use pragmas and inline assembly.

Programming and optimizing DSP C code: Part 2

This second of a five-part series shows how to optimize DSP «kernels,» i.e., inner loops. It also shows how to write fast floating-point and fractional code.

Use ESL synthesis techniques to replace dedicated DSPs with FPGAs

If your application’s not the most compute intensive, you may find that using an FPGA as a replacement for a dedicated DSP is a good idea.

How to use M and Simulink for DSP control and datapath design

This tutorial discusses the tradeoffs of abstraction versus implementability and highlights an approach of embedding M into Simulink to gain some of the advantages of both.

Analysis: BDTI certifies ARC’s H.264 performance

BDTI has certified the H.264 decode performance of the H.264 decode performance of the ARC video subsystem. In this article it reveals the performance numbers and the test process behind them.

Testing and Debugging DSP Systems: Part 2

Part two of this six-part series explains the workings of the JTAG (IEEE 1149.1) boundary-scan technology. It defines the test pins and the test process associated with a JTAG port.

Testing and Debugging DSP Systems, Part 1

Part one of this six-part series introduces the hardware used for debugging, the debugging challenges facing DSP programmers, and debugging methodologies.

Programming and optimizing DSP C code: Part 1

This first of a five-part series introduces the basic principles of writing C code for a DSP processor. It also explains how to profile and optimize code.

Designing a DSP-based Digitally Controlled DC-DC Switching Power Supply: Part 2

The second in a two part tutorial on DSP-based DC-DC digital control comparing two design methodologies: Direct Digital Design and Design by Emulation.

DSP Compensation for Small Loudspeakers

Small loudspeakers and noisy listening environments ruin audio quality. Here’s how psychoacoustic DSP-based algorithms can help.

Signal processing isn’t a commodity

DSP functions are not interchangeable, and that means they wil not become commodties anytime soon.

Fixed vs. floating point: a surprisingly hard choice

Which is better: a fixed-point DSP or a floating-point DSP? The answer may surprise you—and so may the reasons. This article shows how to make the right choice, using two $5 DSPs as examples.

Designing a DSP-based Digitally Controlled DC-DC Switching Power Supply

Part 1 in a tutorial on DSP-based DC-DC digital control comparing two design methodologies: Direct Digital Design and Design by Emulation

Analysis: Freescale’s dual core Audio DSPs

Freescale’s latest audio processor is a dual core DSP packed with features, targeting next generation DVD players and other high end apps. BDTI explains how it works, and how it stacks up against the competition.

Analysis: TI’s three core 65 nm DSP

Texas Instruments’ latest DSP is a three core chip targeting GSM, TD-SCDMA and WiMax base station applications. BDTI expains how it works.

FPGAs vs DSPs: A look at the unanswered questions

BDTI examines how FPGAs and DSPs compare in terms of performance, cost, power and ease of development.

Parallel processing for multi-core DSPs

With a dynamic scheduler, software developers can write applications that can scale in performance by running on an arbitrary number of DSP processors to achieve the desired performance, while using and sharing all processors efficiently.

DSP-based system-on-chip moves speech recognition from the lab to portable devices

Researchers from Tsinghua and Infineon Technologies describe development of a speech recognition system-on-chip for use in consumer applications such as toys, voice-based remote control and speech recorders.

Why Multiprocessor DSP Systems Need CORBA

CORBA enables software components in a multiprocessor system to easily communicate—regardless of what language they are written in, what OS they run on, or where they are located. Even better, COBRA makes it easy to move functionality between DSPs, GPPs, and FPGAs.

Digital Receiver Design: Basics of Software Radio Part 4

The final article in this series on software radio covers digital receiver applications for software radios, including a tracking receiver system, signal intelligence receiver, direction finding system, radar signal processing system, and wireless cellular development system.